A liquid crystal display device employing multi-pixel drive is an example of a liquid crystal display device that deals better with a problem regarding a viewing angle dependency of a γ characteristic. According to the multi-pixel drive, each pixel is made up of two or more sub pixels of different brightness. It is thus possible to deal better with the problem regarding the viewing angle dependency of a viewing angle characteristic, i.e., the γ characteristic.
FIG. 8 shows a configuration example of a pixel of the liquid crystal display device that employs the multi-pixel drive (see, for example, Patent Literature 1).
A pixel P is divided into two sub pixels sp1 and sp2. The sub pixel sp1 includes a TFT 16a, a sub pixel electrode 18a, and a storage capacitance 22a. The sub pixel sp2 includes a TFT 16b, a sub pixel electrode 18b, and a storage capacitor 22b. 
The TFTs 16a and 16b have: respective gate electrodes both connected to a common gate bus line GL; and respective source electrodes both connected to a common source bus line SL. The storage capacitance 22a is formed between the sub pixel electrode 18a and a storage capacitor bus line CsL1. The storage capacitance 22b is formed between the sub pixel electrode 18b and a storage capacitor bus line CsL2. The storage capacitor bus line CsL1 extends so as to be in parallel with the gate bus line GL across the sub pixel sp1. The storage capacitor bus line CsL2 extends so as to be in parallel with the gate bus line GL across the sub pixel sp2.
The storage capacitor bus line CsL1 of the pixel P also serves as a storage capacitor bus line CsL2 of an adjacent pixel P located next to the pixel P across the storage capacitor bus line CsL1, so that a sub pixel sp2 of the adjacent pixel P forms storage capacitance 22b with the storage capacitor bus line CsL1. On the other hand, the storage capacitor bus line CsL2 of the pixel P also serves as a storage capacitor bus line CsL1 of an adjacent pixel P located next to the pixel P across the storage capacitor bus line CsL2, so that a sub pixel sp1 of the adjacent pixel P forms storage capacitance 22a with the storage capacitor bus line CsL2.
With reference to FIGS. 9 and 10, the following description discusses a method for driving the storage capacitor bus lines CsL1 and CsL2 of a display panel of multi-pixel drive type.
As shown in FIG. 9, storage capacitor bus lines CsL (the storage capacitor bus lines CsL1 and CsL2 are collectively referred to as storage capacitor bus lines CsL), which are provided alternately in the active area AA that is the display region, are connected to the respective CS trunk lines bb provided in the region adjacent to the active area AA. The CS trunk lines bb constitute a CS trunk line group BB. The CS trunk line group BB is provided in a region adjacent to one end, i.e., given end, of the active area AA in a direction in which the storage capacitor bus lines CsL extend. Alternatively, it is possible that that CS trunk line groups BB are provided in respective regions, one of which is adjacent to one end, i.e., given end, of the active area AA in a direction in which the storage capacitor bus lines CsL extend and the other of which is adjacent to the other end of the active area AA in the direction.
In a case where a CS trunk line group BB is provided solely in the region adjacent to the one end of the active area AA, the storage capacitor bus lines CsL have one ends connected to the respective CS trunk lines bb. On the other hand, in a case where CS trunk line groups BB are provided in the respective regions adjacent to the ends of the active area AA, the storage capacitor bus lines CsL have (i) one ends connected to the respective CS trunk lines bb provided in the region adjacent to the given end of the active area AA, and (ii) the other ends connected to the respective CS trunk lines bb provided in the region adjacent to the other end of the active area AA. The CS trunk lines bb extend in a direction, i.e., a direction in which the source bus lines SL extend, which is orthogonal to the direction in which the storage capacitor bus lines CsL1 and CsL2 extend.
FIG. 9 illustrates an example in which CS trunk line groups BB, each made up of twelve CS trunk lines bb, are provided in respective regions. A storage capacitor bus line CsL is connected to one CS trunk line bb of each of the CS trunk line groups BB. The twelve (which is equal to the number n (n is an even number) of the CS trunk lines bb of each CS trunk line group BB) storage capacitor bus lines CsL, which are sequentially provided, are connected to respective different CS trunk lines bb of each CS trunk line group BB, and such connection relationships hold true for every set of twelve (i.e., the number n) storage capacitor bus lines.
In a case where a CS trunk line group BB is provided solely in the region adjacent to one end of an active area AA, n storage capacitor bus lines CsL, which are sequentially provided, are connected to respective different CS trunk lines bb of the CS trunk line group BB, and such connection relationships hold true for every set of n storage capacitor bus lines.
Both in a case where the CS trunk line group BB is provided solely in the region adjacent to the one end of the active area AA and in a case where CS trunk line groups BB are provided in the respective regions adjacent to the one and the other end of the active area AA, storage capacitor voltages Vcs as shown in FIG. 10 (in FIG. 10, Vsc1, Vcs2, and so on) are applied to the respective n storage capacitor bus lines CsL sequentially provided. Those of the storage capacitor voltages Ves (in FIG. 10, Vcs1, Vcs2, and so on) which are supplied to respective sub pixels sp1 and sp2 of each pixel P on an odd line via storage capacitor bus lines CsL1 and CsL2 have respective binary-level waveforms that change at same timings and same cycle periods but in different ranges. The storage capacitor voltages Vcs include n/2 pairs of storage capacitor voltages Vcs, which n/2 pairs of storage capacitor voltages Vcs are supplied to respective odd lines of pixels P. The n/2 pairs of the storage capacitor voltages Vcs to be supplied to the respective odd lines of pixels P are set so as to be gradually shifted in phase from one another. In each of the odd lines of pixels P, a gate pulse Vg (in FIG. 10, Vg1, Vg3, and so on) has a pulse period during a given period of corresponding one of the n/2 pairs of storage capacitor voltages Vcs. The pulse period ends at timing when the corresponding one of the n/2 pairs of storage capacitor voltages Vcs rises or falls.
By this, data signals are written down into the odd lines of the pixels P first. After the data signals are written down, storage capacitor voltages Vcs are changed so that different amounts ΔV of electric potentials are (i) fed through to sub pixels sp1 and sp2 of a pixel P which receive an identical data signal, and (ii) added to respective electric potentials of pixel electrodes of the sub pixels sp1 and sp2. This varies luminance of the sub pixels sp1 and sp2 from each other. Average luminance of actual values of voltages which are supplied to liquid crystals during one frame period under influences of storage capacitor voltages Vcs causes the γ characteristic of the entire pixels P to be appropriate in a wide range of viewing angle.
After the odd lines of the pixels P are scanned, then even lines of the pixels P are scanned. However, unlike in the case with scanning of the odd lines of the pixels P, a pair of storage capacitor voltages to be supplied to respective sub pixels sp1 and sp2 of a same pixel P are not arranged to change in level at same timing. Nevertheless, first electric potential changes of pixel electrodes to occur after an end of a gate pulse period are same as those obtained in the case with the scanning of the odd lines of the pixels P. It is therefore possible it is still possible to enhance the γ characteristic.
The main technical feature of the present invention is to enhance the γ characteristic of the entire pixels P by employing changes of the respective different storage capacitor voltages Vcs in varying luminance of the sub-pixels sp1 and sp2 of the pixels P.
The storage capacitor voltages Vcs are supplied via corresponding CS trunk lines bb. Thus, it is arranged so that different storage capacitor voltages Vcs are supplied via the respective CS trunk lines bb of the CS trunk line group. In order that this is achieved, a CS driver (which is not illustrated) supplies, to the respective CS trunk line group, the storage capacitor voltages whose phases have equal umber to the number of the CS trunk lines bb. FIG. 10 illustrates an example in which a CS driver supplies storage capacitor voltages having 12 phases. In a case where the CS trunk line groups are provided to both ends of the active area AA, as shown in FIG. 10, the identical storage capacitor voltages Vcs are supplied via two CS trunk lines bb of the respective CS trunk line groups, which two CS trunk lines bb are connected to a same storage capacitor bus line CsL. By supplying the storage capacitor voltages from the both ends of the active area AA in this way, it is possible to prevent it that in a large-sized liquid crystal screen, interconnect delay causes a waveform of the storage capacitor voltage Vcs to vary from one point to another in the active area AA.